(1) Field of the Invention
The present invention relates to a semiconductor device which includes an output circuit for transmitting output signals on transmission lines such as wires on a printed circuit board.
(2) Description of the Related Art
A signal transmission system includes a CMOS (complementary metal oxide semiconductor) device which is an output circuit for transmitting output signals on transmission lines. The CMOS device uses a p-channel metal-oxide-semiconductor field-effect transistor (which will be called the p-channel MOS FET) to perform a pull-up action, and uses an n-channel metal-oxide-semiconductor field-effect transistor (which will be called the n-channel MOS FET) to perform a pull-down action. In this system, the capacity of wires which are connected to external terminals of the system to which outputs of the output circuit are connected is taken as a load capacity.
In the above signal transmission system, signals are transmitted on the transmission lines by charging and discharging the wires having a certain capacity. For periods in which noise signals are produced due to signal reflection, the timing of the charging and discharging of the wires is allocated. The amplitude of the signal transmitted by the above signal transmission system is so great that high-speed transmission may be hardly provided. Also, the above signal transmission system requires a great amount of power consumption.
In order to realize a high-speed transmission and a small amount of power consumption, it is necessary that the above signal transmission system is provided with an output circuit having a characteristic impedance which is equivalent to a characteristic impedance of the wires. The wires are taken as the signal transmission lines having a characteristic impedance which is constant.
Low-voltage-differential-signal (LVDS) transmission systems have been proposed to allow high-speed signal transmission and small power consumption. The LVDS transmission systems serves to provide long-distance, high-frequency signal transmission capabilities. A standardization of the LVDS transmission systems by the Institute of Electrical and Electronic Engineers (IEEE) is under way.
FIG.5 shows a LVDS transmission system which is given as an example of the above-mentioned LVDS systems.
Referring to FIG.5, the LVDS transmission system comprises an integrated circuit 1 and an integrated circuit 2. An output circuit 3 is provided in the integrated circuit 1. The integrated circuit 1 has external terminals 4 and 5. An input circuit 10 including a differential amplifier is provided in the integrated circuit 2. The integrated circuit 2 has external terminals 8 and 9.
The external terminals 4 and 5 of the integrated circuit 1 and the external terminals 8 and 9 of the integrated circuit 2 are interconnected by wires 6 and 7, respectively. The wires 6 and 7 serve as transmission lines on which differential signals are transmitted.
A terminating resistor 11 between differential input terminals of the input circuit 10 is connected. The terminating resistor 11 has a resistance of 100.OMEGA..
In the LVDS transmission system, shown in FIG.5, the output circuit 3 outputs differential signals, which have a complementary relation, to the wires 6 and 7, and the wires 6 and 7 are connected by the terminating resistor 11 at the differential input terminals of the input circuit 10 in the integrated circuit 2. Thus, the differential signals with a small amplitude are transmitted from the output circuit 3 to the input circuit 10 through the transmission lines 6 and 7.
FIG.6 shows a conceived output circuit which is included in the LVDS transmission system in FIG.5.
Referring to FIG.6, this output circuit has a line from which a level signal DATA from an internal circuit (not shown) is inputted. The output circuit includes an inverter 13 which generates an inverted data signal at an output of the inverter 13 from the data signal DATA at an input of the inverter 13. The output circuit includes an output inverter 14, an output inverter 15, a p-channel metal-oxide-semiconductor field-effect transistor (which will be called the p-channel MOS FET) 16, a p-channel MOS FET 17, an n-channel metal-oxide-semiconductor field-effect transistor (which will be called the n-channel MOS FET) 18, and an n-channel MOS FET 19. A source power voltage VDD is applied to each of the p-channel MOS FETs 16 and 17, and a grounding voltage VSS is applied to each of the n-channel MOS FETs 18 and 19.
In the output circuit, shown in FIG. 6, a resistor 20 with a precise resistance is connected to an output of the output inverter 14, and a resistor 21 with a precise resistance is connected to an output of the output inverter 15. An error of the resistances of the resistors 20 and 21 is not greater than 10%, and the resistors 20 and 21 have such resistances that "ON" resistances of the inverters 14 and 15 can be taken as the resistances of the resistors 20 and 21.
Generally, the "ON" resistances of the p-channel MOS FETs 16 and 17 and the n-channel MOS FETs 18 and 19 have errors which are above 30%, due to manufacturing errors. In the above-mentioned LVDS transmission system, it is required that an error of a reference voltage VOL for a low-level output and an error of a reference voltage VOH for a high-level output are not greater than 10%.
In the output circuit, shown in FIG. 6, the resistors 20 and 21 are provided so as to cancel the errors of the "ON" resistances of the inverters 14 and 15. It is necessary that the errors of the "ON" resistances of the inverters 14 and 15 be less than 10%, to ensure the accuracy of the reference voltage VOL for the low-level output and the reference voltage VOH for the high-level output.
However, a conventional CMOS producing process does not include a step of forming resistors with precise resistances the errors of which are less than 10%. When producing a semiconductor device including the output circuit shown in FIG. 6, it is necessary to add the step of forming the resistors to the conventional CMOS producing process in order to form the resistors 20 and 21 in the output circuit. Therefore, there is a problem in that the cost of the produced semiconductor device is increased because of the added step.